In an era where semiconductor design demands unprecedented speed and innovation, Harald Kröll, Co-Founder and CEO of Chipmind, shares his vision for transforming chip development through “design-aware” AI agents.
In this interview, Eqvista explores Kröll’s journey from digital chip design engineer and SoC product manager to launching Chipmind, addressing key pain points like excessive debugging (90% of engineering time) and fragile project timelines. He highlights how Chipmind flips the creation-to-execution ratio, enabling engineers to innovate while delivering up to 14x speed-ups in real-world tasks, such as duplicating SoC peripherals in just 18 minutes.
Expect discussions on Kröll’s ETH Zurich roots, where he met co-founder Sandro Belfanti, and Chipmind’s edge over generic AI—native EDA tool integration, persistent memory, and adaptability to proprietary environments. The conversation also covers recent $2.5M pre-seed funding, industry challenges, and the future of agentic AI democratizing hardware design.
Harald, What inspired you to launch Chipmind, and what key pain points in the chip design process were you determined to address?
The inspiration came from two distinct realities I faced in the semiconductor industry.
First, as a Digital Chip Design Engineer, I was constantly disappointed by the ratio of creation to execution. I loved the initial spark of creating a new architecture or innovating on a logic problem. But for every hour I spent on that high-value innovation, I had to spend ten hours debugging it, fighting with integration issues, and wrestling with tools. It felt like 90% of my engineering time was being spent on “digital design plumbing.”
Second, as SoC Product Manager, I experienced the pain of the timeline. I saw how fragile schedules sometimes were. Adding even a relatively simple feature—something that seemed small on paper—could blow up our target launch dates by months because of the integration and verification and testing overheads required to ensure it didn’t break the rest of the chip.
We launched Chipmind to solve exactly this: to flip that ratio for engineers so they can innovate more, and to give semiconductor companies and product managers the velocity to add features without blowing up the schedule.
How did your experience at ETH Zurich and your background in both AI and hardware design inform the early direction of Chipmind?
Multiple tracks from my background came into play: chip design research, digital signal processing, and machine learning, as well as SoC product management. ETH Zurich offered a unique environment for end-to-end SoC design—covering every stage from algorithms to dedicated silicon.
Crucially, it was also at ETH where I met my co-founder, Sandro Belfanti. We shared an office during our PhD studies, and that close collaboration became the incubator for our shared engineering philosophy.
This background gave us a unique dual proficiency. We didn’t come at this as AI researchers looking for a use case; we came from chip design industry and research. We started experimenting with pre-trained transformers like GPT-2 back in 2019. We saw the immense potential of the technology right away, but also saw that the results were far from perfect, especially for hardware description languages and chip design.
We understood the deep, hierarchical nature of hardware design—architectures, algorithms, timing, power, layout—and we knew that a generic “AI for code” model wouldn’t work well. It informed our decision to build design-aware agents from day one. We knew that if the AI didn’t understand the difference between a simple variable change and a critical timing violation, no hardware engineer would trust it.
Chipmind focuses on “design-aware” AI agents. Can you explain how your technology differs from generic automation or standard EDA tool enhancements
The distinction lies in the fact that off-the-shelf coding agents are primarily optimized for software development tasks, which limits their autonomy in complex chip design flows.
While generic agents can generate a lot of code, they often lack the structural reasoning required for large designs and struggle to visualize and integrate with the interactions across files and hierarchies. They also face challenges in operating EDA tools and proprietary environments efficiently because they don’t natively understand the flow. Additionally, generic agents typically lack a persistent memory of past decisions or horizontal guidelines, which can lead to repetitive errors in a project context.
Chipmind bridges this gap. Our agents are built with deep design and environment understanding, allowing them to reason structurally about the hardware. They are designed to operate EDA tools natively and, crucially, they solve the “amnesia” problem by retaining memory of past decisions. This allows them to navigate complex, proprietary environments that general-purpose models find difficult to parse.
What are the biggest challenges in adapting AI agents to varied customer design environments and proprietary toolchains?
The biggest challenge is the heterogeneity of the landscape. Every semiconductor company has multiple “secret sauces” — a mix of legacy scripts, custom internal tools, and specific configurations of design and verification flows. There is no standard stack like there is in other industries.
To adapt, we had to build our agents to be environment-agnostic but highly adaptable. They are designed to “read” the local environment—understanding which flags to use for a specific compiler or which directory structure the team prefers—without needing a massive manual integration effort. It’s about building agents that are flexible enough to navigate proprietary chaos without breaking the secure perimeter.
You’ve stated that up to 40% of engineers’ time is spent on repetitive tasks. What quantifiable impact do your agents have in industry pilots or proof-of-concept projects?
The statistic that 40% of time is wasted on repetitive tasks comes from industry research, but in our own deployments, we are seeing impacts that go far beyond just “saving time.” We have achieved a 14x speed-up on real-world chip design tasks.
A major contributor to this speed-up is the automation of verification overhead. Extending testbenches and writing test programs is incredibly tedious work that often slows down the entire team. Our agents can automate the generation and extension of these test environments, handling the grunt work so the engineer can focus purely on the complex edge cases. It turns a process that usually drags on for days into something that happens in minutes.
Can you share a success story or a case study where Chipmind significantly accelerated a customer’s chip design timeline?
I can share a very concrete example from a Digital IC Design Engineer at a European semiconductor company. They were tasked with duplicating a timer peripheral within their SoC — a complex task that required generating the RTL code, extending the testbenches to cover the new block, and running the simulation successfully.
Done manually, this workflow would have taken an entire afternoon — roughly 4 hours of focused engineering time. By using Chipmind Agents, the engineer completed the entire task in just 18 minutes. That represents a 14x speed-up. This is the kind of velocity that directly addresses the slow concept-to-tape-out cycles I hated as a Product Manager; we turned a half-day slog into a coffee-break task.
The semiconductor sector is known for being risk-averse and slow to adopt new technologies. What barriers to adoption have you encountered, and how are you overcoming them?
Generative AI has created a huge demand and business for chips on one side, so also the appetite for investments is growing rapidly on the other side. Semiconductor companies of all sizes are realizing that they must take calculated risks to avoid losing out to faster competition. The risk of missing a market window because of slow, manual verification is now greater than the risk of adopting new tools. We see a mindset shift where speed is becoming a survival metric, and companies are eager to adopt agents not just for efficiency, but to ensure they don’t get left behind in this new gold rush.
We also encounter significant barriers in integration and reliability: There is the ‘Brownfield’ problem: customers fear that a new AI tool won’t work within sometimes complex, 20-year-old legacy environments and get completely lost.
Along with the fundamental need for semiconductor IP protection, we overcome these barriers by architecture. We deploy on-premise or in secure VPCs to protect semiconductor IP. But equally important, our agents are design-aware and tool-agnostic. They don’t require the customer to clean up their entire legacy flow to get started; the agents adapt to their environment, and because they run verification loops autonomously, they provide the deterministic correctness that hardware engineers demand.
How is Chipmind positioning itself in an AI landscape that also includes industry incumbents like Synopsys and Cadence?
We play the role of partners to make existing chip designs and design flows future-proof and ready to enter the AI age. We are building the layer of intelligence that sits on top of their infrastructure. In relation to the incumbents we see ourselves as collaborators and accelerators, not direct competitors to the EDA giants which provide the essential infrastructure—the “compilers, “synthesizers” and “simulators” of our world.
However, those tools are incredibly complex. While incumbents are adding AI features to their specific tools, Chipmind offers cross-functional agents that bridge the gaps between tools—taking data from a simulator, interpreting it, and modifying the design in the editor. We are the “intelligent glue” that makes their powerful engines more accessible and efficient for the human engineer.
Chipmind recently closed a $2.5M pre-seed funding round. How will this investment accelerate your R&D, go-to-market strategy, and industry partnerships?
This funding, led by Founderful, is critical for Chipmind to build our products and hit the market with our partners.
On the R&D side, we are expanding our engineering team here in Zurich, which is currently a buzzing hotspot for AI. With major players like Anthropic, OpenAI, Mera and Google establishing a strong presence here, the density of talent is incredible. We are tapping into this unique ecosystem to bring on the best minds in both Deep Learning and VLSI to develop our core product, Chipmind Agents.
On the go-to-market side, the capital allows us to support more intensive pilot programs. In this industry, high-value enterprise adoption rarely happens via a credit card on a website; it is driven by proving tangible value in the trenches. This funding gives us the runway to embed with key partners, prove the ROI, and turn those pilots into long-term enterprise contracts.
What does success look like for Chipmind in the next 2–3 years, both commercially and technologically?
Success is that we accelerate chip development cycles in semiconductor companies with Chipmind Agents which are capable of making architectural and system-level decisions, orchestrating end-to-end flows from high-level goals without explicit human step-by-step direction—essentially, an L4 chip design agent.
How do you see agentic AI transforming not only semiconductor design but the broader hardware development ecosystem in the coming decade?
There is not one agent or model coming to replace all chip design flows overnight. Instead, the journey will be like for autonomous driving—a decade-long evolution to full concept-to-GDSII or spec-to-GDSII autonomy.
I believe we are moving toward the democratization of hardware design, lowering the barrier so smaller teams can build custom silicon. But beyond just access, the future of the engineering roles involved in the development of a chip will change fundamentally.
We are moving away from the era of manual execution. The new core tasks will be about curating and reviewing multi-agent outcomes instead of solving low-level tasks. Engineers will evolve from “writers of code” to “architects of intelligence,” where their primary value lies in guiding the agents, making high-level design choices, and reviewing the results, rather than fighting with syntax and scripts.
What advice would you give to emerging founders at the intersection of AI and deep tech regarding building meaningful, sustainable impact?
Don’t just look for a place to apply AI; solve a pain you have felt personally.
In deep tech, the customers are the experts. They can smell a generic solution from a mile away. If you haven’t felt the pain of the problem you are solving—like the stress of a slipping tape-out date—you won’t have the intuition to solve it correctly. Build for the workflow, not just the benchmark. The flashiest AI model means nothing if it doesn’t fit into the messy, legacy reality of an engineer’s daily life.
